Parity checking system with reduced usage of I/O pins

Details Parity checking system with reduced usage of I/O pins Parity checking system with reduced usage of I/O pins

1994-07-07

1996-05-14

Beausoliel, Jr., Robert W.

Excavating

G06F 1100

Patent

active

055175147

ABSTRACT:
A data integrity system comprising a plurality of units connected together for the transfer of data between the units. Each said unit comprises data means for receiving data from one or more other units and/or transmitting data to one or more other units, first means, if the unit transmits data to other units, for generating a PARITY OUT signal indicating the parity of all data transmitted to the other units and second means, if the unit is to receive data from other units, for generating a PARITY IN signal indicating the parity of all data being received by the unit from the other units. A third means, located in one of said plurality of units, receives all the PARITY OUT signals and all the PARITY IN signals generated by the plurality of units and detects from all the received PARITY IN signals and all the PARITY OUT signals whether an error had occurred during the transfer of data between the units.

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