Parity checking apparatus with bus for connecting parity devices

Details Parity checking apparatus with bus for connecting parity devices Parity checking apparatus with bus for connecting parity devices

1988-03-31

1992-10-13

Envall, Jr., Roy N.

Excavating

395325, G06F 1110, G06F 1340, G06F 1342

Patent

active

051557355

ABSTRACT:
Apparatus and methods for performing parity checking in an environment in which devices which perform parity checking and those which do not are connected to the same synchronous bus. The bus includes a parity enable line, which carries a parity enable signal indicating that the device transmitting data on the bus is a parity device which provides the parity of the data it transmits, a parity line, which carries the parity of the data being transmitted, and a parity error line which carries a parity error signal indicating whether the receiving device detected a parity error. The data is transmitted in a first bus cycle, the parity enable signal and the parity are transmitted in the following bus cycle, and the receiving device transmits the parity error signal in the next bus cycle after that. The bus interface for each parity device includes a parity generator and logic which generates the parity and parity enable signals and receives the parity error signal when the parity device is transmitting and which receives the parity and parity enable signals and generates the parity error signal when the device is receiving. The apparatus is used with system diagnostic apparatus which records the occurrence of any parity error among devices attached to the bus.

REFERENCES:
patent: 4476527 (1984-10-01), Clayton, IV
patent: 4480307 (1984-10-01), Budde et al.
patent: 4528666 (1985-07-01), Cline et al.
patent: 4621323 (1986-11-01), Mayhew
patent: 4636937 (1987-01-01), Kishi et al.
patent: 4825438 (1989-04-01), Bennett et al.

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