Parity checker circuit

Details Parity checker circuit Parity checker circuit

1985-10-31

1988-05-24

Smith, Jerry

Excavating

G06F 1110

Patent

active

047471069

ABSTRACT:
A parity checker circuit for performing a parity check in the serial transfer of data in an integrated circuit having an odd or even decision circuit receiving sequential bits constituting a data stream and generating an output signal having a level which becomes high or low and representing whether the number of "1" or "0" in the data is odd or even, and a parity flag circuit connected to receive the output signal from the decision circuit and operable in accordance with a write signal received simultaneously with the high or low level output signal and, in response to these signals, for outputting a parity flag indicative of the parity of the data.

REFERENCES:
patent: 2848607 (1958-08-01), Maron
patent: 3024444 (1962-03-01), Barry
patent: 3250900 (1966-05-01), Diamant
patent: 4346474 (1982-08-01), Sze
patent: 4538271 (1985-08-01), Kohs
F. F. Sellers, "Error Detecting Logic for Digital Computers", 1968, pp. 64 and 65.

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