Parity check system in a semiconductor memory

Details Parity check system in a semiconductor memory Parity check system in a semiconductor memory

1974-12-23

1976-07-27

Hecker, Stuart N.

Communications: electrical

Digital comparator systems

235153AM, G11C 700, G11C 2900

Patent

active

039720330

ABSTRACT:
A semiconductor memory includes means for separating the causes of error affecting the addressing and recording of information bits from those affecting check, or parity, bits. The recording words comprise 16 information bits, and are divided into two "bytes", of eight bits each. Each byte is provided with its own check bit; and two half-words of nine bits are recorded at the same address. Each submodule of the memory comprises two printed-circuit cards. The first card supports the integrated memory units wherein, for each word, the information bits of the first byte and the check bit of the second byte are recorded; the second card supports the memory units wherein the information bits of the second byte and the check bit of the first byte are recorded. Since an error cause affecting the control or the addressing circuits mounted on a card does not affect the recording and the addressing circuits of the second card, the recording or addressing of the information bits on one card will differ from the recording and addressing of the related check bit on the other card. Both bytes may be written or read out separately; and the writing or the reading-out signals of the information bits are independent from the writing or reading-out signal of the related check bits for both cards.

REFERENCES:
patent: 3761898 (1973-09-01), Pao
patent: 3858187 (1974-12-01), Lighthall et al.
Hoff, "Application Considerations for Read/Write Memories," Semiconductor Memories, 1971, pp. 11-27.
Tsui, Memory Organization and Operation for Byte-Feature Implementation, IBM Technical Disclosure Bulletin, vol. 15, No. 3, 8/72, pp. 792-794, 530,350,076.

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