Parity bit memory simulator

Details Parity bit memory simulator Parity bit memory simulator

1994-11-29

1996-12-17

Baker, Stephen M.

Excavating

39518507, G06F 1110

Patent

active

055861296

ABSTRACT:
A parity bit memory simulator including a parity bit memory formed of a single bit memory of fixed address length, which replaces the single bit parity RAM of variable address length of conventional memory modules, is connected with its address signal line to the data bus of the memory module so that the parity bit memory provides and stores parity bits for the computer system without changing the circuit layout of the data memory or caring about the capacity of the memory module. A voltage level detector and a refreshing operation detector can be installed in the parity bit memory to improve an error detecting function of a dynamic random access memory module in the parity bit system.

REFERENCES:
patent: 5095485 (1992-03-01), Sato
patent: 5355377 (1994-10-01), Venkidu et al.
patent: 5367526 (1994-11-01), Kong
patent: 5446873 (1995-08-01), Chan

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