Parity bit emulator with write parity bit checking

Details Parity bit emulator with write parity bit checking Parity bit emulator with write parity bit checking

1995-05-19

1997-09-30

Teska, Kevin J.

G06F 1110

Patent

active

056734190

ABSTRACT:
A computer system includes a parity bit emulator circuit which generates a parity bit to be associated with a data byte output by a signal in-line memory module (SIMM) to a CPU. Each parity bit emulator monitors four consecutive write cycles to determine whether the system parity is even or odd, and thereafter monitors each write cycle to determine if a data transfer error has occurred during a write from the CPU to the SIMM. A state machine circuit provides appropriate timing for write and read cycle memory access protocols.

REFERENCES:
patent: 4005405 (1977-01-01), West
patent: 5218691 (1993-06-01), Tuma et al.
patent: 5355377 (1994-10-01), Venkidu et al.
patent: 5367526 (1994-11-01), Kong
patent: 5477553 (1995-12-01), Kong

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