Parellel type nonvolatile semiconductor memory device method of

Details Parellel type nonvolatile semiconductor memory device method of Parellel type nonvolatile semiconductor memory device method of

1996-04-05

1998-08-11

Zarabian, A.

Static information storage and retrieval

Floating gate

Particular biasing

36518506, 36518526, G11C 1604

Patent

active

057936781

ABSTRACT:
On a semiconductor substrate of a first conductive type is formed a well layer of the same conductive type as that of the substrate in electrically separated that is, physically separated and electrically isolated, from the substrate, and a MOS transistor, used as a nonvolatile memory cell, forming a drain region and a source region respectively within the well layer is used as a memory cell. Well layers associated with different columns are connected to each other by a well wiring commonly so that operation voltage different from that of the semiconductor substrate is applied thereto. In the case of data erasing, prescribed positive voltage is applied to a well wiring, and prescribed voltage lower than said positive voltage is applied to a selected word line. In the case of data programming, prescribed negative voltage is applied to the well wiring, prescribed voltage higher than said negative voltage is applied to the selected word line.

REFERENCES:
patent: 4881201 (1989-11-01), Sato et al.
patent: 5402374 (1995-03-01), Tsuruta et al.
patent: 5504706 (1996-04-01), D'Arrigo et al.
patent: 5515319 (1996-05-01), Smayling et al.

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