Parasitic insensitive switched capacitor input structure for a f

Details Parasitic insensitive switched capacitor input structure for a f Parasitic insensitive switched capacitor input structure for a f

1986-02-20

1987-03-03

Mullins, James B.

Amplifiers

Combined with automatic amplifier disabling switch means

330107, 330258, 333173, H03F 108

Patent

active

046478655

ABSTRACT:
An input structure which is parasitic insensitive and allows a fully differential amplifier to receive a single input voltage while maintaining a predetermined common-mode input voltage is provided. A single input voltage is charged onto two capacitors which are coupled in series between the input voltage and a predetermined common-mode reference voltage terminal during a first time period. During a second time period, the two capacitors are reconfigured so that each capacitor is connected between the reference voltage terminal and a predetermined one of the inputs of the fully differential amplifier. Due to the balanced nature of the input structure, all parasitic capacitance error terms are rejected by the differential amplifier.

REFERENCES:
patent: 4574250 (1986-03-01), Senderowicz
Senderowicz, "A Family of Differential NMOS Analog Circuits for a PCM Codec Filter Chip," IEEE Journal of Solid-State Circuits, vol. SC-17, No. 6, Dec. 1982, pp. 1014-1023.

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