Parasitic insensitive capacitor in d/a converter

Details Parasitic insensitive capacitor in d/a converter Parasitic insensitive capacitor in d/a converter

2000-06-19

2002-09-17

Dinkins, Anthony (Department: 2831)

Electricity: electrical systems and devices

Electrostatic capacitors

Fixed capacitor

C361S312000, C361S303000

Reexamination Certificate

active

06452778

ABSTRACT:

BACKGROUND OF THE INVENTION
Switched capacitor structures typically utilize a plurality of capacitors having the plates thereof switched from the input of a differential amplifier to another voltage or to the output of the previous stage, which also incorporates the output of a differential amplifier. These capacitors are normally formed on an integrated circuit from a combination of semiconductor material, metal and oxide. Each capacitor is comprised of a plurality of layers, including the interconnect layers. However, the interconnect layers, depending upon the fabrication thereof, have associated therewith parasitic capacitance. This parasitic capacitance is a function of the layout, the thickness of the oxides, etc. This causes manufacturing variations between capacitors.
Typically, capacitors are fabricated based upon a “unit” value. For example, a unit capacitor may constitute one capacitor in a binary weighted string wherein the first capacitor in the string is a single unit value the second is comprised of two units, the third four units, etc. The way that the capacitors are manufactured is to actually fabricate unit capacitors and interconnect the capacitors together. However, the interconnection can have parasitics associated therewith which results in the capacitor being greater or less than a multiple of a unit value capacitor.
SUMMARY OF THE INVENTION
The present invention disclosed and claimed herein, in one aspect thereof, comprises a capacitor structure in a integrated circuit. A semiconductor substrate is provided having a first face upon which the semiconductor integrated circuit is formed with a first conductive layer disposed over a portion of the first face of the semiconductor substrate and separated therefrom by a first insulating layer to form the lower plate of the capacitor. A second conductive layer is disposed over a portion of and less than all of the first conductive layer and separated therefrom by a second insulating layer to form the upper plate of the capacitor. A third conductive layer is disposed above the first and second conducting layers and separated from the first conducting layer by a third insulating layer, the third conducting layer having an opening therein of substantially the same shape as the second conducting layer and wherein the peripheral edges of the opening are substantially aligned with the peripheral edges of the second conducting layer. A conductive interconnect is disposed above the third conductive layer and separated therefrom by a fourth insulating layer and connected on at least a portion thereof to the second conducting layer, the interconnect extending over the third conductive layer such that the third conductive layer separates the interconnect from the first conductive layer.


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