Television – Camera – system and detail – Solid-state image sensor
Reexamination Certificate
1997-11-05
2001-05-15
Garber, Wendy R. (Department: 2612)
Television
Camera, system and detail
Solid-state image sensor
C348S250000, C348S310000, C250S2140AG, C330S267000, C377S060000
Reexamination Certificate
active
06233012
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention pertains to integrated circuit designs providing features which reduce the capacitance on input lines to certain circuit elements such as charge amplifiers.
Parasitic input capacitance is of great importance in charge readout performance. In many integrated circuits containing arrays of data elements (e.g., memory devices having arrays of memory cells and imagers having arrays of pixels), amplifiers read out charge stored on the individual elements of the array. Ideally, the readout should be performed rapidly and accurately. Unfortunately, a large input line capacitance requires that some of the charge initially injected to the amplifier be used to charge the “input line capacitor.” This of course slows the readout time and reduces or increases that amount of charge provided to the amplifier.
From the perspective of a charge amplifier, the main effects of input capacitance are (1) time response, (2) gain, and (3) output linearity. If C
L
, C
R
A, and &dgr;Q are the input capacitance, the feedback capacitance, the voltage gain, and the injected charge respectively, the output of the charge amplifier is inversely proportional to C
R
according to the relation &Dgr;V
o
=&dgr;Q/(C
L
/A)+(1+(1/A))C
R
) and the time response is proportional to the loop gain, C
R
/(C
R
+C
L
). From the previous analysis, two observations can be drawn: (i) the output linearity is seriously affected by the input capacitance for low amplifier gain, and (ii) gain and speed of the amplifier are traded off as in a generic negative feedback system. Thus, the speed of the system benefits greatly from a reduction on the input line capacitance.
For applications as in the field of CMOS optical sensors, the input line capacitance, Cr, is composed of the diffusion and metal capacitances of the line as shown in FIG.
1
. There, a photodiode
8
is connected to a charge amplifier input line
10
via a switch
12
. Photodiode
8
may be provided in a single pixel of a photodiode array of a CMOS imager, for example. When switch
12
is closed, charge stored on photodiode
8
is provided over input line
10
to a capacitor
16
. Charge accumulated on capacitor
16
provides a voltage across the plates of the capacitor, which voltage may be read by an amplifier
14
. The detected voltage should represent the charge stored on photodiode
8
. A switch
18
is provided to allow reset of photodiode
8
. During reset (after readout), switch
18
is closed so that the output of charge integrate toward it is provided to line
10
, thereby resetting photodiode
8
while switch
12
is closed. This procedure resets photodiode
8
to reference voltage, V
R
.
Input line
10
includes two sources of parasitic capacitance: a metal capacitance illustrated as an idealized capacitor
20
and a diffusion capacitance illustrated as an idealized capacitor
22
. The metal capacitance is created by the dielectric between the metal input line and the grounded substrate or other conductive features insulated from but proximate to line
10
. Its effect is manifested when a potential change is applied to line
10
, thereby changing the charge stored on the capacitor electrodes (i.e., the metal line and the substrate). The diffusion capacitance is created by a p-n junction at the interface of a diffusion (e.g., a photodiode diffusion) and a surrounding well or bulk region. When the diffusion is charged or discharged (as by injecting charge onto line
10
), the capacitor defined by a p-n junction depletion region is charged or discharged. For most of integrated circuit designs in production today, about one half of the input line capacitance is due to the metal line (with the other half provided by the diffusion(s)).
In view of the above, it is clear that device performance could be significantly improved by designs that reduce input line capacitance from the diffusion and/or metal line components.
SUMMARY OF THE INVENTION
To reduce the input line capacitance with respect to the ground, the present invention provides circuitry which drives a metal shield provided underneath, and in relatively close proximity to, a metal input line. Preferably, the shield is driven by a buffer directly connected to the input line. Thus, the potential of the metal shield follows that of the input line thereby reducing the capacitive charge stored on the metal line. Of course, an amplifier is also coupled to the input line. If the speed of the buffer is greater than that of the amplifier, the input metal capacitance may be largely neglected. To further improve the system performance, diffusions of the input line may be placed in wells whose potential is driven by the buffer.
In one aspect, the invention may be characterized as an integrated circuit including the following features: (a) an amplifier for reading the output of individual cells in the integrated circuit; (b) an input line connecting the amplifier to at least one of the individual cells; (c) a shield line provided underneath and capacitively coupled to the input line; and (d) a circuit element conductively connecting the shield line to the input line, such that the circuit element provides a potential to the shield line which follows an input potential on the input line. This reduces the capacitive load on the input line. In one embodiment, the circuit element is a unity gain buffer such as a pull-up amplifier.
If the integrated circuit is a CMOS imager, the individual cells are pixels, for example. If the integrated circuit is a memory array, the individual cells are storage elements.
In one preferred embodiment, the shield line is a metal line. Depending upon where the input line resides in the integrated circuit, the metal line may be provided between two metallization layers, beneath a first metallization layer, etc. If the individual cells contain diffusions in wells, the shield line may be conductively coupled to the wells. This can reduce the diffusion capacitance associated with the individual cells of the array.
In another aspect, the invention may be characterized as a method of reducing a capacitive load on an input line to an amplifier on an integrated circuit. This method may be characterized as including the following events: (a) operating the integrated circuit such that the signal on a cell of the integrated circuit is provided on the input line to the amplifier; and (b) providing the signal to a shield line provided beneath the input line and capacitively coupled thereto, such that the signal on the shield line follows the signal on the input line to reduce the capacitive load on the input line.
Yet another aspect of the invention provides a system for producing an image of an object. This system includes an imager including a low capacitance input line of the type described above and one or more components for outputting an image resulting from the outputs of one or more pixels. The image may be a photograph in the case of a digital camera for example.
These and other features and advantages of the invention will be described below in the Detailed Description section with reference to the appended drawings.
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patent: 4902886 (1990-02-01), Smisko
patent: 5019702 (1991-05-01), Ohzu et al.
patent: 5101174 (1992-03-01), Hynecek
patent: 5652150 (1997-07-01), Wadsworth
patent: 5652622 (1997-07-01), Hycenek
patent: 5831258 (1998-11-01), Street
patent: 5880993 (1999-03-01), Kramer
patent: 6111606 (2000-08-01), Ikeda
Bisio Marco
Guerrieri Roberto
Tartagni Marco
Galanthay Theodore E.
Garber Wendy R.
Jorgensen Lisa K.
STMicroelectronics Inc.
Vu Ngoc-Yen
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