Parasitic capacitance cancellation circuit

Details Parasitic capacitance cancellation circuit Parasitic capacitance cancellation circuit

1994-08-08

1995-07-18

Ngo, Ngan V.

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

With contact or metallization configuration to reduce...

257507, 257526, 257593, H01L 2712, H01L 2702

Patent

active

054344468

ABSTRACT:
A parasitic capacitance cancellation circuit for a direct bonded silicon-on-insulator integrated circuit includes one or more transistors fabricated silicon-on-insulator; a silicon substrate region outside the transistor(s) having a parasitic capacitance to be cancelled; a bootstrap terminal connected to the region outside the transistor(s); and a unity gain buffer responsive to the output of the transistor(s) and having its output connected to the bootstrap terminals for providing a voltage to the region outside the transistor(s) which follows the voltage developed on the parasitic capacitance and nullifies the parasitic capacitance.

REFERENCES:
patent: 4341990 (1982-07-01), Davis
patent: 4623854 (1986-11-01), Kuraishi
patent: 5047734 (1991-09-01), Newell et al.
patent: 5185585 (1993-02-01), Newell et al.

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