Parasitic capacitance canceling circuit

Details Parasitic capacitance canceling circuit Parasitic capacitance canceling circuit

2001-01-30

2002-11-12

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Gating

Signal transmission integrity or spurious noise override

C327S493000

Reexamination Certificate

active

06480052

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method and/or architecture for a capacitor designed into an integrated circuit generally and, more particularly, to a method and/or architecture for reducing or eliminating effects of a parasitic capacitor related to the capacitor.
BACKGROUND OF THE INVENTION
Integrated circuit designs may use multiple conductive layers to form parallel plate capacitors isolated from a substrate. One design approach is to form an intended capacitor using two conductive layers used in the integrated circuit design process. For example, a polysilicon layer may be used to for a bottom plate and a metal layer may be used to for a top plate of the intended capacitor. Where three or more conductive layers are available, the capacitance can be increased by interconnecting every other layer of the multiple conductive layers.
A problem with parallel plate capacitor designs in integrated circuits is that a parasitic capacitance is formed between the substrate and the nearest conductive layer. The parasitic capacitance causes unwanted effects in the intended capacitor. For example, the parasitic capacitance may introduce noise pickup from the substrate into the intended capacitor. In another example, the parasitic capacitance can increase an effective capacitive load of the intended capacitor thus leading to unwanted attenuation of a signal.
SUMMARY OF THE INVENTION
The present invention concerns a circuit than may be used in an integrated circuit capacitor design. The circuit generally comprises a multilayer capacitor and a buffer. The multilayer capacitor may be configured as (i) a first capacitance, (ii) a second capacitance, and (iii) a third capacitance in series between the first capacitance and the second capacitance. The buffer may be configured to maintain a constant voltage across the third capacitance to isolate the first capacitance from the second capacitance.
The objects, features and advantages of the present invention include providing a method and/or architecture for implementing an integrated circuit capacitor that may (i) reduce the effects of a parasitic capacitance, (ii) reduce noise coupling from a substrate, and/or (iii) reduce signal attenuation.


REFERENCES:
patent: 5559667 (1996-09-01), Evans
patent: 5733309 (1998-03-01), Kroll et al.
patent: 6317378 (2001-11-01), Savignac et al.

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