Parametrized waveform processor for gate-level power analysis to

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364578, G06F 1750

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057681457

ABSTRACT:
A power analysis tool includes a power arc identifier that extracts power arc information from simulation results including the occurrence time of each arc. These occurrence times are then stored in an arc occurrence database on which power analysis can be performed after the simulation has occurred. This allows a user to specify different circuit groupings on which to perform power analysis without requiring the circuit to be resimulated. The tool also includes a power calculator that converts average current, propagation delay, and intrinsic delay stored in a power data library into positive load current and negative load current for a cell. From these currents an "internal cell" current is derived which is related to the two load currents by a formula. Decomposing the cell currents into load currents and internal cell currents permits more accurate power analysis, thereby allowing the circuit designer or router to modify the design to better accommodate the power consumption by either using a lower power cell to reduce the internal cell current or change the loading on the cell to reduce the loading current. The cell currents are grouped together by a power group processor based on the occurrence times of the arcs as stored in the arc occurrence database. The internal cell currents for a given cell are combined together as are the positive and negative load currents. The currents from various cells can then be combined in any manner according to user defined groupings. From these combined currents the Vdd and Vss current waveforms are formed.

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