Parametric test system and method

Details Parametric test system and method Parametric test system and method

1998-03-02

1999-12-28

Ballato, Josie

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

324763, G01R 3102, G01R 3126

Patent

active

060086645

ABSTRACT:
A system and method for reducing voltage stabilization time in a leakage current test system, and thereby reducing the time for measuring leakage currents in the I/O pins of an IC chip including CMOS DRAMs is disclosed. The method and system of the present invention accelerates leakage current testing time by precharging the capacitance of the I/O pins under test to a voltage near the settled voltage level, before measuring leakage current at the I/O pin contact points of packaged IC chips and assembled IC modules, and indicating when an I/O pin is defective.

REFERENCES:
patent: 4092589 (1978-05-01), Chau et al.
patent: 5223792 (1993-06-01), El-Ayat et al.
patent: 5539694 (1996-07-01), Rouy
patent: 5745405 (1998-04-01), Chen et al.

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