Parameterized cells for generating dense layouts of VLSI circuit

Details Parameterized cells for generating dense layouts of VLSI circuit Parameterized cells for generating dense layouts of VLSI circuit

1996-08-16

1999-07-06

Teska, Kevin J.

Boots, shoes, and leggings

364490, 364489, 364488, G06F 1700, G06F 1750

Patent

active

059204869

ABSTRACT:
The invention provides a technique, given a netlist containing a description of the terminal connections and the length and width of each device in a circuit, for automatically producing a layout for each device in that circuit.

REFERENCES:
patent: 4700316 (1987-10-01), Nair
patent: 4713773 (1987-12-01), Cooper et al.
patent: 4914612 (1990-04-01), Beece et al.
patent: 5029102 (1991-07-01), Drumm et al.
patent: 5432707 (1995-07-01), Leung
patent: 5666288 (1997-09-01), Jones et al.
patent: 5737236 (1998-04-01), Maziasz et al.
patent: 5818727 (1998-10-01), Sekiguchi

Affiliated with

Also associated with

Rating

Parameterized cells for generating dense layouts of VLSI circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Parameterized cells for generating dense layouts of VLSI circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Parameterized cells for generating dense layouts of VLSI circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-904218