Parameter variation probing technique

Details Parameter variation probing technique Parameter variation probing technique

2000-12-28

2003-03-18

Cuneo, Kamand (Department: 2829)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C324S763010, C324S1540PB

Reexamination Certificate

active

06535013

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a parameter variation probing technique and more particularly, to a technique for probing parameter variations in an integrated circuit chip
BACKGROUND OF THE INVENTION
There are inherent parameter variations in integrated circuit chips, such as VLSI (Very Large Scale Integration) chips. As the system clock frequencies of such chips increase, the cycle times decrease. Fluctuations in gate delays due to intra-die parameter variations, interconnect loading variations, interconnect coupling variations, temperature fluctuations, and local supply voltage variations are becoming more and more significant as the cycle times decrease. Furthermore, as the elements sizes and interconnect line widths decrease, these variations increase. In order to prevent functional race conditions and to improve the speed of the integrated circuit chip elements, these variations have been compensated for by providing an additional design margin in the timing calculations. As the speeds of the integrated circuit chips increase, this additional design margin becomes an ever increasing percentage of the cycle time of the chips, thereby severely limiting the design space available to a designer, resulting in longer design cycles and lower product target frequencies.
Furthermore, gate delay variations due to intra-die device parameter variations, such as channel length and threshold voltage in MOSFET circuit elements, are presumed to account for roughly 25% of the minimum-delay (hold) margin required in a design and more than 15% of that required for maximum-delay (setup). The amount of gate delay variations of MOSFET gate elements has been estimated from knowledge of the VLSI fabrication process device parameter variation specifications. However, due to probing difficulties, few direct measurements have been made to validate the accuracy of these presumptions
It would therefore be desirable to have an easily obtainable, objective, the historical accumulation of chip element and interconnect parameter variations across a chip for progressive process generations. Such historical perspective would allow for better strategic engineering predictions regarding the feasibility of current design technologies using future advanced process technologies. Device parameter variations on these advanced process technologies will likely get worse as feature sizes shrink and accordingly, it would be desirable to have an objective measurement technique to replace the educated guesses that have been employed up until this time. Such a technique would improve design space, reduce design time, and enhance target speed performance.
BRIEF DESCRIPTION OF THE DRAWINGS
The foregoing and a better understanding of the present invention will become apparent from the following detailed description of example embodiments and the claims when read in connection with the accompanying drawings, all forming a part of the disclosure of this invention. While the foregoing and following written and illustrated disclosure focuses on disclosing example embodiments of the invention, it should be clearly understood that the same as by way of illustration and example only and the invention is not limited thereto. The spirit and scope of the present invention of limited only by the terms of the appended claims.


REFERENCES:
patent: 4799259 (1989-01-01), Ogrodski
patent: 5811985 (1998-09-01), Trimberger et al.
patent: 5999009 (1999-12-01), Mitsui
patent: 6177845 (2001-01-01), Moll
patent: 6239603 (2001-05-01), Ukei et al.
U.S. patent application Ser. No. 09/606,484, Stinson et al., filed Jun. 29, 2000.

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