Parameter tolerant PLL synthesizer

Details Parameter tolerant PLL synthesizer Parameter tolerant PLL synthesizer

1990-12-14

1991-10-08

Mis, David

Oscillators

Automatic frequency stabilization using a phase or frequency...

Particular error voltage control

331 1A, 331 16, 331 25, H03L 7093

Patent

active

050558030

ABSTRACT:
In a PLL synthesizer, the tolerance to gain and component variations is greatly reduced when the gain of the loop in increased above that which the loop was initially designed for and if the third order loop symmetric ratio is reduced to a value within the range of 2.0 to 2.5. Higher order loops based on the third order symmetric ratio range have correspondingly lower transmission pole frequency to open unity gain frequency ratios.

REFERENCES:
patent: 4516083 (1985-05-01), Turney
patent: 4546329 (1985-10-01), Unger
patent: 4559505 (1985-12-01), Suarez et al.
patent: 4952889 (1990-08-01), Irwin et al.
Graham et al., "The Synthesis of `Optimum` Transient Response: Criteria and Standard Forms", AIEE Transactions, Nov. 1953, pp. 273-288.
Underhill et al., "The Effect of the Sampling Action of Phase Comparators on Frequency Synthesizer Performance", Proceedings of the 33rd Annual Frequency Symposium, 1979, pp. 449-457.
Przedpelski, "PLL Primer - Part IV", RF Design, Nov. 1987, pp. 88, 90, 93, 94, 96.

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