Parallelized coherent read and writeback transaction processing

Details Parallelized coherent read and writeback transaction processing Parallelized coherent read and writeback transaction processing

1995-03-31

1996-12-03

Swann, Tod R.

395472, 395471, G06F 1208, G06F 1300

Patent

active

055817297

ABSTRACT:
A multiprocessor computer system is provided having a multiplicity of sub-systems and a main memory coupled to a system controller. An interconnect module, interconnects the main memory and sub-systems in accordance with interconnect control signals received from the system controller. At least two of the sub-systems are data processors, each having a respective cache memory that stores multiple blocks of data and a respective master cache index. Each master cache index has a set of master cache tags (Etags), including one cache tag for each data block stored by the cache memory. Each data processor includes a master interface having master classes for sending memory transaction requests to the system controller. The system controller includes memory transaction request logic for processing each memory transaction request by a data processor. The system controller maintains a duplicate cache index having a set of duplicate cache tags (Dtags) for each data processor. Each data processor has a writeback buffer for storing the data block previously stored in a victimized cache line until its respective writeback transaction is completed and an Nth+1 Dtag for storing the cache state of a cache line associated with a read transaction which is executed prior to an associated writeback transaction of a read-writeback transaction pair. Accordingly, upon a cache miss, the interconnect may execute the read and writeback transactions in parallel relying on the writeback buffer or Nth+1 Dtag to accommodate any ordering of the transactions.

REFERENCES:
patent: 4345309 (1982-08-01), Arulpragasam et al.
patent: 4620275 (1986-10-01), Wallach et al.
patent: 4812972 (1989-03-01), Chastain et al.
patent: 4926317 (1990-05-01), Wallach et al.
patent: 5058006 (1991-10-01), Durdan et al.
patent: 5113514 (1992-05-01), Albonesi et al.
patent: 5222224 (1993-06-01), Flynn et al.
patent: 5226146 (1993-07-01), Milia et al.
patent: 5276852 (1994-01-01), Callander et al.
patent: 5319766 (1994-06-01), Thaller et al.
patent: 5361267 (1994-11-01), Godiwala et al.
patent: 5375220 (1994-12-01), Ishikawa
patent: 5388224 (1995-02-01), Maskas
Sweazey, Paul et al., "A Class of Compatible Cache Consistency Protocols and their Support by the IEEE Futurebus", The Cache Coherence Problem in Shared-Memory Multiprocessors: Hardware Solutions, p. 228-237 1993.
Sweazey, Paul, "VLSI Support for Copyback Caching Protocols on Futurebus", Proceedings of the Computer Design-ICCD '88, 1988 International Conference, p. 240-246 1988.
Sweazey, Paul, "Shared Memory Systems on the Futurebus", Proceedings of COMPCON Spring '88, IEEE Computer Society Int'l. Conference, p. 505-511 1988.

Affiliated with

Also associated with

Rating

Parallelized coherent read and writeback transaction processing does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Parallelized coherent read and writeback transaction processing , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Parallelized coherent read and writeback transaction processing will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-794479