Parallelism with variable partitioning and threading

Details Parallelism with variable partitioning and threading Parallelism with variable partitioning and threading

2007-09-06

2010-06-15

Coleman, Eric (Department: 2183)

Electrical computers and digital processing systems: processing

Processing architecture

Array processor

Reexamination Certificate

active

07739481

ABSTRACT:
A programmable device includes multiple function unit control memories connected to multiple sequencers through an address selection network. Sequencers are dynamically assigned to function unit control memories allowing intermediate level including statement level and control construct level parallelism. A programmable device can be partitioned by reassigning function unit control memories to different sequencers operable to execute Very Long Instruction Word (VLIW) instructions.

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