Parallel variable bit encoder

Details Parallel variable bit encoder Parallel variable bit encoder

1999-08-13

2001-01-09

JeanPierre, Peguy (Department: 2819)

Coded data generation or conversion

Digital code to digital code converters

To or from variable length codes

C370S465000

Reexamination Certificate

active

06172626

ABSTRACT:

FIELD OF THE INVENTION
The invention relates generally to encoding and decoding of digital data and more particularly to a method of segmenting data using a barrel shifter, the data for transmission using an STS-1 protocol.
BACKGROUND OF THE INVENTION
Barrel shifters are known electronic circuits. A barrel shifter comprises a buffer and a means for providing a movable window at an output thereof. In a recirculating barrel shifter, the buffer is circular and when the window keeps moving around the circular buffer—its start location incremented between cycles.
Barrel shifters are used for data decompression when variable bit compression schemes are used. Barrel shifters are also used in arithmetic function implementations, circular buffer circuits, parallel processing, control systems, and so forth. The use of barrel shifters in different applications has been included in patent applications since at least as early as Feb. 22, 1982. The use of barrel shifter circuits for encoding and decoding as described in some of the patents below, applies to compression and decompression algorithms where a plurality of bits is compressed into a smaller number of bits and look up tables are necessary to determine a shift amount for each processing cycle.
Examples of U.S. patents describing circuits or systems using barrel shifters include U.S. Pat. No. 5,650,781 entitled Apparatus for decoding variable length codes; U.S. Pat. No. 5,646,874 entitled Multiplication/multiplication-accumulation method and computing device; U.S. Pat. No. 5,646,873 entitled Barrel shifter device and variable-length decoder; U.S. Pat. No. 5,642,115 entitled Variable length coding system; U.S. Pat. No. 5,634,065 entitled Three input arithmetic logic unit with controllable shifter and mask generator; U.S. Pat. No. 5,621,405 entitled Variable-length decoding apparatus using relative address; U.S. Pat. No. 5,619,200 entitled Code table reduction apparatus for variable length decoder; U.S. Pat. No. 5,619,198 entitled Number format conversion apparatus for signal processing; U.S. Pat. No. 5,604,499 entitled Variable-length decoding apparatus; U.S. Pat. No. 5,600,847 entitled Three input arithmetic logic unit with mask generator; U.S. Pat. No. 5,594,927 entitled Apparatus and method for aligning data transferred via DMA using a barrel shifter and a buffer comprising of byte-wide, individually addressabe FIFO circuits; U.S. Pat. No. 5,590,350 entitled Three input arithmetic logic unit with mask generator; U.S. Pat. No. 5,561,690 entitled High speed variable length code decoding apparatus; U.S. Pat. No. 5,557,734 entitled Cache burst architecture for parallel processing, such as for image processing; U.S. Pat. No. 5,557,563 entitled Data processing method and apparatus including iterative multiplier; U.S. Pat. No. 5,555,202 entitled Low-power, high-performance barrel shifter; U.S. Pat. No. 5,553,010 entitled Data shifting circuit capable of an original data width rotation and a double data width rotation; U.S. Pat. No. 5,542,074 entitled Parallel processor system with highly flexible local control capability, including selective inversion of instruction signal and control of bit shift amount; U.S. Pat. No. 5,532,949 entitled Barrel shifter; U.S. Pat. No. 5,529,071 entitled Increasing dynamic range with a barrel shifter; U.S. Pat. No. 5,526,296 entitled Bit field operating system and method with two barrel shifters for high speed operations; U.S. Pat. No. 5,517,436 entitled Digital signal processor for audio applications; U.S. Pat. No. 5,509,129 entitled Long instruction word controlling plural independent processor operations; U.S. Pat. No. 5,499,382 entitled Circuit and method of bit-packing and bit-unpacking using a barrel shifter; U.S. Pat. No. 5,481,583 entitled Higher order preinterpolator for backprojection; U.S. Pat. No. 5,479,527 entitled Variable length coding system; U.S. Pat. No. 5,477,477 entitled Data shifting circuit by utilizing MOS barrel shifter; U.S. Pat. No. 5,471,628 entitled Multi-function permutation switch for rotating and manipulating an order of bits of an input data byte in either cyclic or non-cyclic mode; U.S. Pat. No. 5,465,223 entitled Barrel shifter; U.S. Pat. No. 5,465,222 entitled Barrel shifter or multiply/divide IC structure; U.S. Pat. No. 5,463,638 entitled Control device for interface control between a test machine and multi-channel electronic circuitry, in particular according to boundary test standard; U.S. Pat. No. 5,457,723 entitled Barrel shifter having CMOS structure integrated on MOS integrated circuits; U.S. Pat. No. 5,450,607 entitled Unified floating point and integer datapath for a RISC processor; U.S. Pat. No. 5,432,512 entitled Apparatus for decoding variable length codes; U.S. Pat. No. 5,420,584 entitled Data converter with barrel shifter; U.S. Pat. No. 5,416,731 entitled High-speed barrel shifter; U.S. Pat. No. 5,404,138 entitled Apparatus for decoding variable length codes; U.S. Pat. No. 5,343,195 entitled Variable length codeword decoding apparatus; U.S. Pat. No. 5,381,454 entitled Circuit and method of resetting a data compressor/decompressor; U.S. Pat. No. 5,309,156 entitled Variable-length code decoding device; U.S. Pat. No. 5,295,250 entitled Microprocessor having barrel shifter and direct path for directly rewriting output data of barrel shifter to its input; U.S. Pat. No. 5,282,152 entitled Integer-based 18-bit RGB to 5-bit gray scale conversion device and method therefor; U.S. Pat. No. 5,262,971 entitled Bidirectional shifter; U.S. Pat. No. 5,247,627 entitled Digital signal processor with conditional branch decision unit and storage of conditional branch decision results; U.S. Pat. No. 5,245,637 entitled Phase and frequency adjustable digital phase lock logic system; U.S. Pat. No. 5,245,338 entitled High-speed variable-length decoder; U.S. Pat. No. 5,241,490 entitled Fully decoded multistage leading zero detector and normalization apparatus; U.S. Pat. No. 5,237,667 entitled Digital signal processor system having host processor for writing instructions into internal processor memory; U.S. Pat. No. 5,223,832 entitled Serial data transmission circuit; U.S. Pat. No. 5,222,241 entitled Digital signal processor having duplex working registers for switching to standby state during interrupt processing; U.S. Pat. No. 5,220,670 entitled Microprocessor having ability to carry out logical operation on internal bus; U.S. Pat. No. 5,206,940 entitled Address control and generating system for digital signal-processor; U.S. Pat. No. 5,187,678 entitled Priority encoder and floating-point normalization system for IEEE 754 standard; U.S. Pat. No. 5,173,695 entitled High-speed flexible variable-length-code decoder; U.S. Pat. No. 5,161,117 entitled Floating point conversion device and method; U.S. Pat. No. 5,155,698 entitled Barrel shifter circuit having rotation function; U.S. Pat. No. 5,146,220 entitled Data conversion method and apparatus for converting undefined length data to fixed length data; U.S. Pat. No. 5,144,573 entitled Barrel shifter with parity bit generator; U.S. Pat. No. 5,130,941 entitled Dynamic barrel shifter; U.S. Pat. No. 5,130,940 entitled Barrel shifter for data shifting; U.S. Pat. No. 5,081,700 entitled Apparatus for high speed image rotation; U.S. Pat. No. 5,060,242 entitled Non-destructive lossless image coder; U.S. Pat. No. 5,045,993 entitled Digital signal processor; U.S. Pat. No. 5,040,138 entitled Circuit for simultaneous arithmetic calculation and normalization estimation; U.S. Pat. No. 5,031,135 entitled Device for multi-precision and block arithmetic support in digital processors; U.S. Pat. No. 5,029,121 entitled Digital filter processing device; U.S. Pat. No. 5,027,306 entitled Decimation filter as for a sigma-delta analog-to-digital converter; U.S. Pat. No. 4,983,958 entitled Vector selectable coordinate-addressable DRAM array; U.S. Pat. No. 4,980,853 entitled Bit blitter with narrow shift register; U.S. Pat. No. 4,979,175 entitled State metric memory arrangement for a viterbi decoder; U.S. Pat. No. 4,979,139 entitled Arithmetic unit for exponential

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