Parallel variable bit encoder

Details Parallel variable bit encoder Parallel variable bit encoder

1997-10-03

1999-10-26

Young, Brian

Coded data generation or conversion

Digital code to digital code converters

To or from variable length codes

370465, H03M 740

Patent

active

059736283

ABSTRACT:
A data segmentation circuit is disclosed for use in DS3/STS-1 mapping. The data segmentation circuit uses a circular data buffer to store data for mapping. A recirculating barrel shifter is used for extracting data from within the buffer. A counter moves the barrel shifter window zero, one, five, or eight bits to align the barrel shifter output as necessary to extract a next datum for a next payload envelope location. Data stuffing is then performed. Control circuitry for providing throttling and bit stuffiing as required in an STS-1 information payload is disclosed.

REFERENCES:
patent: 5268935 (1993-12-01), Mediavilla et al.
patent: 5272703 (1993-12-01), Peters
patent: 5327126 (1994-07-01), Beanland
patent: 5337334 (1994-08-01), Molloy
patent: 5461380 (1995-10-01), Peters et al.
patent: 5548534 (1996-08-01), Upp

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