Communications: electrical – Digital comparator systems
Patent
1976-04-02
1977-05-10
Zache, Raulfe B.
Communications: electrical
Digital comparator systems
G06F 504
Patent
active
040231445
ABSTRACT:
A high speed parallel to serial digital converter includes a data shift rster, a control shift register and control circuitry. During a control cycle a control input comprising a set of control bits in parallel form is converted by the control shift register into serial form. The serialized control bits are coupled to a register load selector which responds to the control bits to appropriately signal the control circuitry so that at the end of the control cycle the converter will commence either another control cycle or a data cycle. During a data cycle an input data word comprising data bits in parallel form is converted by the data shift register into serial form. At the end of a data cycle timing circuitry signals the control circuitry to commence a reset cycle during which the converter is reset to commence another control cycle.
REFERENCES:
patent: 3277446 (1966-10-01), Diamant et al.
patent: 3333253 (1967-07-01), Sahulka
patent: 3395400 (1968-07-01), De Witt et al.
Rubens G. J.
Sciascia R. S.
The United States of America as represented by the Secretary of
Zache Raulfe B.
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