Parallel-to-serial converter

Details Parallel-to-serial converter Parallel-to-serial converter

1987-03-09

1988-07-19

Heyman, John S.

Electrical pulse counters, pulse dividers, or shift registers: c

Shift register

Particular output circuit

377 54, 364900, G11C 700, G11C 1500

Patent

active

047590424

ABSTRACT:
A parallel-to-serial converter is described, comprising a shift register into which a data word can be loaded in parallel and then shifted out serially. As the data is shifted out, a string of zeros is shifted in. When a predetermined number of zeros is detected, a flip-flop is set at the next clock beat. This switches the shift register into its parallel load mode so that, at the next again clock beat the shift register is parallel loaded with the next data word. The detection of the predetermined number of zeros and the setting up of the shift register occur in different clock periods, allowing the clock period to be reduced, thus increasing the speed of operation.

REFERENCES:
patent: 4023144 (1977-05-01), Koenig
patent: 4216391 (1980-08-01), Gehrig et al.
patent: 4581740 (1986-04-01), Kinoshita
patent: 4630295 (1986-12-01), Kamuro et al.

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