Coded data generation or conversion – Digital code to digital code converters – Parallel to serial
Patent
1995-02-09
1997-10-21
Hoff, Marc S.
Coded data generation or conversion
Digital code to digital code converters
Parallel to serial
365238, H03M 900
Patent
active
056801270
ABSTRACT:
A parallel-to-serial conversion device capable of improved space efficiency has a corner turn memory array provided in an input section of the device to perform parallel-to-serial conversion by writing in the row direction of the input section and by reading out in the column direction of the input section, write section for selectively writing data into a first pair of memory cells of said corner turn memory array; and readout section for simultaneously reading data from a second pair of memory cells which are different from the first pair of memory cells.
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Paul Chow, et al, "A pipelined Distributed Arithmetic PFFT Processor", IEEE Transactions on Computers. vol. C-32. No. 12, Dec. 1983, pp. 1128-1136.
Masataka Matsui, et al.,"200MHz Video Compression Macrocells Using Low-Swing Differential Logic", IEEE International Solid State Circuits Conference.
Matsui Masataka
Nagamatsu Tetsu
Hoff Marc S.
Kabushiki Kaisha Toshiba
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