Parallel-to-serial CMOS data converter with a selectable bit wid

Details Parallel-to-serial CMOS data converter with a selectable bit wid Parallel-to-serial CMOS data converter with a selectable bit wid

1998-01-09

1999-11-09

Young, Brian

Coded data generation or conversion

Digital code to digital code converters

Parallel to serial

H03M 900

Patent

active

059823097

ABSTRACT:
A high-speed parallel-to-serial CMOS data transmitter uses a D Flip-flop matrix architecture to combine a shift scheme with a selection scheme to serialize parallel bit data. Data is partially serialized through multi data paths at a much lower frequency and a time-division multiplex scheme selects one bit from each data path allowing for pipelined data processing. The CMOS architecture uses selective load clock mode switching allowing different word bit widths to be processed simply by adjusting the frequency of a loading clock.

REFERENCES:
patent: 4901076 (1990-02-01), Askin et al.
patent: 5055842 (1991-10-01), Mueller
patent: 5247652 (1993-09-01), Uda
patent: 5319369 (1994-06-01), Major et al.
patent: 5379038 (1995-01-01), Matsumoto
patent: 5648776 (1997-07-01), Widmer
patent: 5654707 (1997-08-01), Matsumoto
patent: 5774079 (1998-07-01), Zirngibl
patent: 5798720 (1998-08-01), Yano

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