Parallel-to-serial binary data converter with multiphase and mul

Details Parallel-to-serial binary data converter with multiphase and mul Parallel-to-serial binary data converter with multiphase and mul

1978-06-30

1980-08-19

Shaw, Gareth D.

Boots, shoes, and leggings

235 92CV, G06F 504

Patent

active

042187583

ABSTRACT:
Parallel binary data from a data source are processed for serialization by circuitry including parallel data registers, a clock ring that provides four phases, and a two phase counter which is operated so that the two phases are in quadrature to each other, and each of its two phases changes count value only once for each complete cycle of the four phase clock ring. The counter has two sets of output signals which are used to select pairs of parallel bits in one of two data registers. The selected bits from the data registers are sampled in serial time by a phase clock pulse from the clock ring, interleaved and processed to form a stream of serialized data bits.

REFERENCES:
patent: 3090034 (1963-05-01), Fredericks et al.
patent: 3312948 (1967-04-01), Capozzi
patent: 3417377 (1968-12-01), Vietor et al.
patent: 3609391 (1971-09-01), Hatano
patent: 3796961 (1974-03-01), Tripp
patent: 3863226 (1975-01-01), Ryburn
patent: 3898627 (1975-08-01), Hooker et al.
patent: 3986046 (1976-10-01), Wunner
patent: 4023144 (1977-05-01), Koenig

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