Parallel-to-parallel converter including common multiple...

Details Parallel-to-parallel converter including common multiple... Parallel-to-parallel converter including common multiple...

1998-09-23

2001-02-06

Young, Brian (Department: 2819)

Coded data generation or conversion

Digital code to digital code converters

Byte length changed

C341S100000, C341S101000

Reexamination Certificate

active

06184808

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a parallel-to-parallel converter used in a serial communication system for optical communications.
2. Description of the Related Art
In the field of serial communications such as optical communications, encoding techniques such as adding redundant bits to each signal for preventing consecutive high levels and low levels from taking place and keeping the ratio of high levels to low-levels constant are generally used. With a popular encoding technique called 8B10B, 8-bit data are transformed into 10-bit data before they are transmitted. On the receiving side, the received 10-bit data are transformed back into 8-bit data before they are decoded.
In a prior art serial communication system, a transmitter is formed by an 8B10B encoder and a 10 bit-to-1 bit (10-to-1) multiplexer, and a receiver is formed by a 1 bit-to-10 bit (1-to-10) demultiplexer and a 10B8B decoder. This will be explained later in detail.
In the prior art system, the transformation of a parallel signal into a serial signal and vice versa is carried out on the basis of a unit of 10 bits. Thus, the 10-to-1 multiplexer and the 1-to-10 demultiplexer are indispensable for converting the parallel signal into the serial signal and vice versa.
On the other hand, a tree-type multiplexer (or demultiplexer) adapted to a high speed parallel-to-serial (or serial-to-parallel) conversion by means of 2-to-1 multiplexers (or 1-to-2 demultiplexers) are known.
However, it is impossible to apply the high speed tree-type multiplexer or demultiplexer to the prior art serial communication system, because each circuit element is based on a 2-input and 1-output or 1-input and 2-output arrangement.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a parallel-to-parallel converter suitable for use in a high speed serial communication system.
According to the present invention, in a parallel-to-parallel converter for converting an “m”-bit parallel signal into an “n”-bit parallel signal, a common multiple register has a bit width which is a common multiple of “m” and “n”.
An input selector is connected to an input of the common multiple register, and writes the “m”-bit parallel signal into the common multiple register at a predetermined frequency. An output selector is connected to an output of the common multiple register, and reads the “n”-bit parallel signal from the common multiple register at a frequency equal to m
times the predetermined frequency.


REFERENCES:
patent: 4499454 (1985-02-01), Shimada
patent: 5321400 (1994-06-01), Sasaki et al.
patent: 5726990 (1998-03-01), Shimada et al.
patent: 5-114925 (1993-05-01), None
patent: 6-104954 (1994-04-01), None
patent: 7-273742 (1995-10-01), None
patent: 8-221248 (1996-08-01), None

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