Parallel testing of CPU cache and instruction units

Excavating

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

39518306, 39518318, 371 211, 371 221, G06F 1100, G06F 1130

Patent

active

059405880

ABSTRACT:
A method for testing CPU microprocessors having internal cache involves testing one IU and a portion of the internal cache, then loading a cache test routine to the tested portion of internal cache and causing that routine to be executed by the tested IU to test the previously untested portion of the internal cache while simultaneously testing any other IUs and circuitry on the CPU microprocessor. A system is disclosed for performing the method.

REFERENCES:
patent: 4553201 (1985-11-01), Pollaek, Jr.
patent: 4891811 (1990-01-01), Ash et al.
patent: 5055774 (1991-10-01), Catt
patent: 5155844 (1992-10-01), Cheng et al.
patent: 5398325 (1995-03-01), Chang et al.
patent: 5479413 (1995-12-01), Sicola et al.
patent: 5539878 (1996-07-01), Kikinis

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Parallel testing of CPU cache and instruction units does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Parallel testing of CPU cache and instruction units, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Parallel testing of CPU cache and instruction units will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-323598

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.