Parallel testing in a per-pin hardware architecture platform

Data processing: measuring – calibrating – or testing – Testing system – Including program set up

Reexamination Certificate

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Details

C702S108000, C702S117000, C702S120000, C324S073100, C714S724000, C714S742000

Reexamination Certificate

active

07853425

ABSTRACT:
Provided is a method and system for testing a DUT. The system includes a plurality of testing devices for interacting with the DUT and conducting a plurality of different tests on the DUT, and a computer-readable memory for storing computer-executable instructions defining the plurality of tests to be conducted by the testing device on the DUT. A scheduler component designates at least a first test and a second test from the plurality of tests to be conducted on the DUT in parallel, wherein said designating is based at least in part on content of the computer-executable instructions defining the first test and the second test. And a controller initiates the first test and the second test to be conducted in parallel and initiating at least a third test sequentially relative to at least one of the first and second tests.

REFERENCES:
patent: 7240258 (2007-07-01), Hayes
patent: 7680619 (2010-03-01), Lei
patent: 2004/0093180 (2004-05-01), Grey et al.
patent: 2005/0102589 (2005-05-01), Park et al.
patent: 2006/0195747 (2006-08-01), Pramanick et al.
patent: 2008/0164894 (2008-07-01), Kim et al.

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