Optics: eye examining – vision testing and correcting – Spectacles and eyeglasses – With antiglare or shading
Reexamination Certificate
1998-05-20
2001-03-06
Brown, Glenn W. (Department: 2873)
Optics: eye examining, vision testing and correcting
Spectacles and eyeglasses
With antiglare or shading
C324S754090
Reexamination Certificate
active
06196677
ABSTRACT:
FIELD OF THE INVENTION
The present invention is generally directed to a method for testing an integrated circuit, and more particularly to a method for parallel testing a plurality of integrated circuits.
BACKGROUND
Delivery of high quality parts and controlling production costs are often competing objectives for semiconductor manufacturers as they are for other types of businesses. One area where these objectives compete is in the testing of wafers and integrated circuit packages.
Various test techniques include sequential chain testing or “scan” testing, and built-in self-testing (BIST). Testers that use scan and/or BIST techniques typically require moderate incremental hardware costs. However, the yield rate for circuits subjected to scan and BIST tests alone is not great enough to proceed from wafer test to package assembly because some circuits may pass the scan and BIST tests and still be inoperable when packaged. Therefore, machine-mode parallel pattern testing and parametric tests are performed after the scan and BIST tests. The drawback to machine-mode and parametric testing is that they require a full complement of tester channels for signals and power. The result is that duplication of expensive test equipment is required to increase test throughput using conventional parallel test technology with microprocessor and VLSI devices.
Conventional parallel testing of microprocessor circuits has been found to be expensive relative to the corresponding increase in testing throughput. As explained above, a large part of the expense is driven by the hardware requirements for machine-mode and parametric testing. In addition, relatively short test times may not justify the hardware expense.
SUMMARY OF THE INVENTION
The present invention is directed to a method and system for testing a plurality of integrated circuits. According to one embodiment of the invention, a method and system for testing a plurality of integrated circuits using a probe card having a plurality of circuit sites is provided. First, a group of the plurality of integrated circuits is registered or associated with the probe card and a first-pass test is performed in parallel on each registered or associated integrated circuit in the group using a first number of signal channels for each circuit site. A particular one of the integrated circuits in the group which passed the first-pass test is then selectively registered or associated with a particular one of the circuit sites, and a second-pass test is performed on the particular one integrated circuit using a second number of signal channels greater than the first number. In this manner, the use of test system resources may be optimized with expensive second-pass tests (e.g., performance tests) only being performed on circuits passing less-expensive first-pass tests (e.g., BIST and scan tests).
The above summary of the present invention is not intended to describe each illustrated embodiment or every implementation of the present invention. The figures in the detailed description which follow more particularly exemplify these embodiments.
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Advanced Micro Devices , Inc.
Brown Glenn W.
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