Parallel switching architecture for multiple input/output

Details Parallel switching architecture for multiple input/output Parallel switching architecture for multiple input/output

2008-07-08

2008-07-08

Vu, Huy D (Department: 2619)

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

C370S386000, C370S411000, C370S412000, C370S419000

Reexamination Certificate

active

07397808

ABSTRACT:
A multiple input/output-queued(MIOQ) switch is presented. This MIOQ switch comprises a (k,m)-dimensional crossbar fabric having k ingress lines and m egress lines; N input buffers at each input; M output buffers at each output; N×k interconnection networks each of which is able to move a packet from each input to one of the k egress lines; and m×M interconnection networks each of which is able to move the arrived packet at output from the m egress lines to one of the M(wherein M is m or N) output buffers. The multiple input/output-queued(MIOQ) switch according to the present invention requires no “speed-up”. Performance matches the performance of an output-queued switch.

REFERENCES:
patent: 7136381 (2006-11-01), Battle et al.
patent: 2001/0038634 (2001-11-01), Dally et al.
patent: 2001-37202 (2001-05-01), None
Chuang, et al. “Matching Output Queueing with a Combined Input Output Queued Switch”, IEEE J. Select. Areas Commun., vol. 17, pp. 1030-1039, Dec. 1999.
Iyer, et al., “Analysis of a packet switch with memories running slower that the line-rate”, IEEE INFOCOM 2000, vol. 2, pp. 529-537, Mar. 2000.

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