Pulse or digital communications – Repeaters – Testing
Patent
1996-04-02
1998-07-07
Butler, Dennis M.
Pulse or digital communications
Repeaters
Testing
395559, 375373, G06F 104
Patent
active
057782172
ABSTRACT:
A parallel signal processing device for high speed timing recovery in a high speed transfer network includes a plurality of data sampling processors (DSP), a central phase-error processor (CPP), and a recovered clock phase adjuster (RCPA. The sampling of transfer data, processing of sampling data, and adjustment of the recovered clock are executed by a plurality of data sampling processors for producing phase difference signals which are then transferred separately to a central phase-error processor. Phase-error adjustment signals for each data sampling processor are produced by the central phase-error processor, and the recovered clock phase for each data sampling processor is adjusted by the recovered clock phase adjuster according to the phase-error. Because the data sampling, phase processing, and adjustment of the recovered clock are simultaneously and parallelly processed by each set of data sampling processors, the high speed recovered clock is readily updated and the data is correctly read by the receiver.
REFERENCES:
patent: 5329559 (1994-07-01), Wong et al.
patent: 5642386 (1997-06-01), Rocco, Jr.
patent: 5668830 (1997-09-01), Georgiou et al.
Butler Dennis M.
Lite-On Communications Corp.
Lite-On Communications, Inc.
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