Parallel shift and add circuit and method

Details Parallel shift and add circuit and method Parallel shift and add circuit and method

1993-11-29

1995-02-14

Mai, Tan V.

Boots, shoes, and leggings

364786, G06F 738, G06F 750

Patent

active

053901355

ABSTRACT:
An apparatus for combining the contents of an X register, shifted by m places, with the contents of a Y register to generate a result Z. The functional unit can also be configured to perform parallel operations on sub-operands in the X and Y registers. The division of the apparatus into sub-operands is controlled by a mask which specifies the boundary of the sub-operands. The shifting operation is accomplished by multiplexers that connect the p.sup.th bit of the X register to the adder stage that operates on bit Y.sub.p-m of the Y register. Circuitry is provided at the boundary of the sub-operands to prevent the bit signals corresponding to the X register from being routed across a sub-operand boundary. Similarly, circuitry is provided for preventing the carry output of an adder stage that operates on one sub-operand from being propagated to an adder stage that operates on another sub-operand.

REFERENCES:
patent: 4707800 (1987-11-01), Montrone et al.
patent: 4768160 (1988-08-01), Yokoyama
patent: 4914617 (1990-04-01), Putrino et al.
patent: 5047975 (1991-09-01), Patti et al.
patent: 5189636 (1993-02-01), Patti et al.

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