Parallel/serial scan system for testing logic circuits

Details Parallel/serial scan system for testing logic circuits Parallel/serial scan system for testing logic circuits

1985-10-23

1987-12-01

Atkinson, Charles E.

Excavating

324 73R, G01R 3128

Patent

active

047109335

ABSTRACT:
A testable logic circuit includes parallel registers (72)-(80) for interfacing with a common internal bus (70). The parallel registers (72)-(80) are individually addressable by an address decoder (104) for storage of test vectors therein. These test vectors are then applied to associated logic circuits. Individual shift register latches (92)-(102) are provided at imbedded locations therein. The shift register latches are interfaced with a serial data link to allow serial loading of data therein. The parallel latches function in both the test mode to store test vectors for application to the associated logic and also in the operational mode for storage of logic data. Use of parallel registers increases the speed at which data is scanned into the device.

REFERENCES:
patent: 4063080 (1977-12-01), Eichelberger et al.
patent: 4503537 (1985-03-01), McAnney
patent: 4519078 (1985-05-01), Komonytsky
patent: 4567593 (1986-01-01), Bashaw
patent: 4602210 (1986-07-01), Fasang et al.
Generalized Scan Test Technique for VLSI Circuits, IBM Technical Disclosure Bulletin, vol. 28, No. 4, Sep. 1985, pp. 1600-1604.

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