Parallel-serial conversion circuit and data receiving system

Coded data generation or conversion – Digital code to digital code converters – Parallel to serial

Reexamination Certificate

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Details

C341S100000

Reexamination Certificate

active

07990294

ABSTRACT:
A parallel-serial conversion circuit includes: a plurality of data terminals each receiving a data signal; a selection circuit configured to select at least one of the data signals received through the plurality of data terminals; a first latch circuit configured to latch an output from the selection circuit based on a clock signal; a replica selection circuit configured to select one of a plurality of signals and output the selected signal; and a timing-signal generating circuit configured to generate a timing signal for controlling the selection circuit based on the output from the replica selection circuit, wherein the output from the replica selection circuit is latched based on the clock signal.

REFERENCES:
patent: 6335696 (2002-01-01), Aoyagi et al.
patent: 6928496 (2005-08-01), Okajima
patent: 7215263 (2007-05-01), Dietrich et al.
patent: 7369069 (2008-05-01), Usugi et al.
Behzad Razavi, Design of Integrated Circuits for Optical Communications, International Edition 2003, Jan. 1, 2003, pp. 333-339.

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