Parallel scrambler used in sonet data transmission

Details Parallel scrambler used in sonet data transmission Parallel scrambler used in sonet data transmission

1990-11-28

1992-11-10

Swann, Tod R.

Cryptography

Particular algorithmic function encoding

380 49, 380 50, 380 44, H04K 100

Patent

active

051630923

ABSTRACT:
A data scrambler circuit which adds the SONET polynomial 1+X.sup.6 +X.sup.7 to data in a parallel format to thereby reduce circuitry clock rates to one-eighth the line rate, which reduces power consumption and simplifies timing constraints. A circuit embodiment includes a first series of flip-flops connected to generate the polynomial and a second series of flip-flops for holding the generated polynomial. The parallel data is added to the held polynomial by a series of exclusive OR gates.

REFERENCES:
patent: 4202051 (1980-05-01), Davida et al.
patent: 4531022 (1985-07-01), Pioli
patent: 4736419 (1988-04-01), Roe
patent: 4965881 (1990-10-01), Dilley
patent: 4977593 (1990-12-01), Ballance

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