Semiconductor device manufacturing: process – Including control responsive to sensed condition – Electrical characteristic sensed
Reexamination Certificate
1998-10-30
2001-06-05
Le, Vu A. (Department: 2824)
Semiconductor device manufacturing: process
Including control responsive to sensed condition
Electrical characteristic sensed
37, 37, C324S073100
Reexamination Certificate
active
06242269
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to testing of integrated circuits using parallel scan paths and particularly relates to testing those integrated circuits using serial to parallel and parallel to serial registers to move test information to and from the integrated circuit.
2. Description of the Related Art
Cost effective testing of today's complex integrated circuits is extremely important to semiconductor manufacturers from a profit and loss standpoint. The increases in complexity of state-of-the-art integrated circuits is being accompanied by an ever increasing difficulty to test the integrated circuits. New test techniques must be developed to offset this increasing integrated circuit test cost, otherwise further advancements in future integrated circuit technology may be blocked. One emerging technology that is going to accelerate the complexity of integrated circuits even more is intellectual property cores. These cores will provide highly complex pre-designed circuit functions such as; DSPs, CPUs, I/O peripherals, memories, and mixed signal A/D and D/A functions. These cores will exist in a library and can be selected and placed in an integrated circuit to quickly provide a complex circuit function. The low cost testing of integrated circuits that contain highly complex core functions will be a significant challenge
SUMMARY OF THE INVENTION
The present invention provides a way to amplify test data input to and output from an integrated circuit by use of pad resident circuits described as parallel scan distributors, PSDs, and parallel scan collectors, PSCs. The scan distributor circuits amplify the number of parallel serial data inputs to the integrated circuit's functional circuitry, and the scan collector circuits amplify the number of parallel serial data outputs from the integrated circuit's functional circuitry.
Additionally, the invention provides a way to test complex cores or core circuits embedded within integrated circuits by reuse of scan distributor circuits and scan collector circuits located at the I/O terminals of the core. In this aspect of the present invention, core resident scan distributor and collector circuits amplify the test data input to and output from the core circuitry, similar to that described for the integrated circuit having no core circuits.
Further, the invention provides a way concurrently to test core and non-core circuitry within an integrated circuit. In this aspect of the present invention, the scan distributor and collector circuits residing at the bond pads of the integrated circuit are serially linked with scan distributor and collector circuits residing at core I/O terminals to provide massive parallel test data input to and output from circuitry within the integrated circuit.
The invention described below facilitates parallel scan testing by use of the scan distributor and scan collector circuits. The scan distributor circuit is basically a serial-input parallel-output shift register, and the scan collector circuit is basically a parallel-input serial-output shift register. While these distributor and collector circuits can be of any bit length, one embodiment shows the distributor and collector circuits being 10 bits deep. With 10 bit deep distributor and collector circuits, the number of scan paths each pad can access is multiplied by a factor of 10. By amplifying the number of scan paths a pad can access, the functional circuitry of the integrated circuit can be partitioned into many more shorter scan paths, reducing the test time of the integrated circuit by reducing the test data shift in/shift out time. For example, using 10 bit scan distributor and collector circuits, an integrated circuit with 200 bond pads (100 bond pad pairs) available for transferring test data can concurrently access 1000 parallel scan paths.
REFERENCES:
patent: 4312067 (1982-01-01), Shirasaka
patent: 4791358 (1988-12-01), Sauerwald et al.
patent: 5054024 (1991-10-01), Whetsel
Bassuk Lawrence J.
Le Vu A.
Luu Pho
Telecky Frederick J.
Texas Instruments Incorporated
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