Parallel sampled multi-stage decimated digital loop filter...

Details Parallel sampled multi-stage decimated digital loop filter... Parallel sampled multi-stage decimated digital loop filter...

2004-10-14

2008-09-02

Payne, Daivd C. (Department: 2611)

Pulse or digital communications

Synchronizers

Synchronizing the sampling time of digital data

C375S354000, C375S376000

Reexamination Certificate

active

07421050

ABSTRACT:
The present invention utilizes a parallel sampled multi stage decimated digital loop filter for clock and data recovery function. In particular, the present invention provides multiple sampling clocks, with these clocks having sampling clock phases separated in time. These clocks are used in conjunction with multiple data detectors and phase detectors to efficiently process received analog signals in a decimated loop filter system.

REFERENCES:
patent: 5247544 (1993-09-01), LaRosa et al.
patent: 6307906 (2001-10-01), Tanji et al.
patent: 6526112 (2003-02-01), Lai
patent: 6636120 (2003-10-01), Bhakta et al.
patent: 7076377 (2006-07-01), Kim et al.
patent: 7127017 (2006-10-01), Evans et al.
patent: 7257169 (2007-08-01), Shahar et al.
patent: 2002/0131539 (2002-09-01), Li et al.
patent: 2005/0239398 (2005-10-01), Lai

Affiliated with

Also associated with

Rating

Parallel sampled multi-stage decimated digital loop filter... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Parallel sampled multi-stage decimated digital loop filter..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Parallel sampled multi-stage decimated digital loop filter... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3992405