Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
2001-07-25
2003-05-20
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S161000, C327S286000
Reexamination Certificate
active
06566924
ABSTRACT:
FIELD OF THE INVENTION
The present invention is generally related to timing in an integrated circuit. In particular, the present invention is related to controlling clock skew in an integrated circuit.
BACKGROUND OF THE INVENTION
In modern, high-performance digital circuits, precise timing is of paramount importance. Slight clock uncertainties can cause momentary, spurious signals which can become magnified as they propagate through a complex digital circuit, often with unpredictable and disastrous results. If such uncertainties are not carefully controlled, they can quickly lead to catastrophic failure or inoperativeness of the digital circuit.
Tiny differences in clock outputs coupled with propagation delays across the complex web of conducting pathways (or traces) on a printed circuit board are one source of timing uncertainty. The source of timing uncertainty effects are well-known to those of ordinary skill in the art, and is typically referred to as clock skew.
Broadly speaking, clock skew is the difference in time delay from a clock input to each of its loads. Clock skew includes the delay arising from the propagation of signals in a printed circuit board across various traces to respective components, which use clock signals as inputs.
For example,
FIG. 3
shows that MY_CLK takes 4 ns to travel to a clock input for FF
1
, but MY_CLK takes 12 ns to travel to a clock input for FF
2
. In this case, there is a 8 ns clock skew for FF
2
. The clock skew for FF
2
must satisfy the timing constraint for FF
2
in order for FF
2
to timely latch the data from FF
1
. If the delay between FF
1
and FF
2
is greater than the clock skew for FF
2
, then the clock skew for FF
2
satisfies the timing constraint for FF
2
, and FF
2
will latch the data from FF
1
on a MY_CLK pulse. If the delay between FF
1
and FF
2
is less than the clock skew for FF
2
, then FF
2
will latch the DATA input on a MY_CLK pulse, as if FF
1
were not in the circuit.
Clock skew places limitations on the speed and performance of high-speed digital devices and must be taken into account in the design of such devices. As clock frequencies are increased aggressively in high performance designs, clock skew constraints become increasingly stringent. In GHz-clocked microprocessors, clock skews are often required to be smaller than 50 ps.
It may be possible to design a clock network having close to zero skew using CAD tools during the design of an integrated circuit. However, uncontrollable manufacturing processing, voltage and temperature (PVT) variations, which generally cannot be accounted for during the design of an integrated circuit, can cause clock skew to reach unacceptable levels. The PVT variations can be as large as 25%, causing significant clock skew. Therefore, on-chip circuitry is needed for controlling clock skew.
SUMMARY OF THE INVENTION
The present invention provides a method and on-chip circuitry for controlling clock skew to satisfy timing constraints for a semiconductor integrated circuit.
In one respect, the present invention includes a self tuning circuit comprising the following: a flip flop connected to a delay path and having a flip flop clock input; a first up-counter connected to the flip flop and having a first up-counter output; a second up-counter connected to the flip flop and the output of the first up-counter, wherein the second up-counter includes a second up-counter output; and an on-purpose delay element connected to the second up-counter output. The on-purpose delay element possesses a clock input and a clock output. The clock output is connected to a latch and the flip flop clock input, and the on-purpose delay element is operable to receive a clock signal on the clock input and transmit either a delayed clock signal or a non-delayed clock signal to the latch and flip flop clock input.
The on-purpose delay element is operable to delayed the clock signal when clock skew for the latch fails to satisfy a delay path timing constraint for that latch. Also, the on-purpose delay element is operable to transmit a non-delayed clock signal when the clock skew satisfies the timing constraint for the latch.
In another respect, the present invention provides a method of controlling clock skew for a plurality of latches in a semiconductor integrated circuit. The method includes the following steps: determining whether clock skew for a first latch satisfies a timing constraint; when the timing constraint is not satisfied, delaying a clock signal latching the latch by one time unit; and pushing the delay to a second latch connected to the first latch. The step of delaying a clock signal can further include repeatedly delaying a clock signal by one time unit and counting each time unit. The clock signal is repeatedly delayed until the timing constraint is satisfied or the total number of counted time units is equal to 2
n
where n is the number of bits in an n-bit up counter counting each time unit.
The present invention provides a self-tuning circuit and method for controlling clock skew to satisfy timing constraints for a semiconductor integrated circuit. Due to circuit imperfections caused during manufacturing, design techniques for meeting timing constraints may be insufficient for satisfying stringent timing constraints. The present invention accounts for manufacturing imperfections by providing an on-chip solution for controlling clock skew to satisfy circuit timing constraints.
REFERENCES:
patent: 4755704 (1988-07-01), Flora et al.
patent: 5313501 (1994-05-01), Thacker
patent: 5394024 (1995-02-01), Buckenmaier et al.
patent: 5506878 (1996-04-01), Chiang
patent: 5742798 (1998-04-01), Goldrian
patent: 5744991 (1998-04-01), Jeffereson et al.
patent: 5751665 (1998-05-01), Tanoi
patent: 5852640 (1998-12-01), Kliza et al.
patent: 5883534 (1999-03-01), Kondohl et al.
patent: 6130566 (2000-10-01), Yokomizo
patent: 6225843 (2001-05-01), Taniguchi et al.
patent: 6320436 (2001-11-01), Fawcett et al.
patent: 6323714 (2001-11-01), Naffziger et al.
Chang Norman
Lee Keunmyung
Lin Shen
Nakagawa Osamu
Xie Weize
Callahan Timothy P.
Hewlett--Packard Development Company, L.P.
Nguyen Hai L.
LandOfFree
Parallel push algorithm detecting constraints to minimize... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Parallel push algorithm detecting constraints to minimize..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Parallel push algorithm detecting constraints to minimize... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3016698