Parallel pulse processing and data acquisition for high speed, l

Details Parallel pulse processing and data acquisition for high speed, l Parallel pulse processing and data acquisition for high speed, l

1990-04-12

1992-09-22

Lall, Parshotam S.

Boots, shoes, and leggings

364486, 364550, 395550, 395725, 395800, G01R 2902, H03K 519

Patent

active

051503131

ABSTRACT:
A digitally synchronized parallel pulse processing and data acquisition system for a flow cytometer has multiple parallel input channels with independent pulse digitization and FIFO storage buffer. A trigger circuit controls the pulse digitization on all channels. After an event has been stored in each FIFO, a bus controller moves the oldest entry from each FIFO buffer onto a common data bus. The trigger circuit generates an ID number for each FIFO entry, which is checked by an error detection circuit. The system has high speed and low error rate.

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