Static information storage and retrieval – Floating gate – Multiple values
Reexamination Certificate
2005-04-19
2005-04-19
Phan, Trong (Department: 2818)
Static information storage and retrieval
Floating gate
Multiple values
C365S185220, C365S185240
Reexamination Certificate
active
06882567
ABSTRACT:
Write operations that simultaneously program multiple memory cells on the same word line in an MBPC Flash memory employ word line voltage variation, programming pulse width variation, and data-dependent bit line and/or source line biasing to achieve uniform programming accuracy across a range of target threshold voltages. A first type of write operations reaches different target threshold voltages during different time intervals, but uses word line signals that optimize threshold voltage resolution regardless of the target threshold voltage. A second type uses bit line and/or source line biases that depend on the multi-bit data values being written so that different memory cells reach different target threshold voltage at about the same time. Source line biasing can also reduce bit line leakage current through unselected memory cells during read or verify operations. A memory includes divided source lines that permit separate data-dependent source biasing. During or at the end of write operations, remedial programming sequences can adjust the threshold voltages of memory cells that program slowly.
REFERENCES:
patent: 5596527 (1997-01-01), Tomioka et al.
patent: 5751635 (1998-05-01), Wong et al.
patent: 6104636 (2000-08-01), Tada
patent: 6259627 (2001-07-01), Wong
Millers David T.
Multi Level Memory Technology
Phan Trong
LandOfFree
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