Parallel programming method of memory words and corresponding ci

Details Parallel programming method of memory words and corresponding ci Parallel programming method of memory words and corresponding ci

1996-09-30

1998-07-14

Nelms, David C.

Static information storage and retrieval

Floating gate

Particular biasing

3651852, 36518523, G11C 1134

Patent

active

057814740

ABSTRACT:
A method for the parallel programming of memory words in electrically programmable non-volatile semiconductor memory devices comprising at least one matrix of floating gate memory cells with corresponding drain terminals heading columns or bit lines of the matrix and supplied during the programming stage with a drain voltage which is boosted with respect to a supply voltage (Vcc). During the parallel programming stage the supply voltage is used as a drain voltage. Switching is provided between the supply using the drain voltage or the supply voltage during the transient between single word programming and parallel programming.

REFERENCES:
patent: 5357463 (1994-10-01), Kinney
patent: 5537350 (1996-07-01), Larsen et al.
patent: 5546339 (1996-08-01), Oyama
patent: 5576990 (1996-11-01), Camerlenghi et al.
Zales et al., "Intel flash EPROM for in-system reprogrammable nonvolatile storage," Microproccessors and Microsystems, vol. 14, No. 8, Oct. 8, 1990, London, pp. 543-549.

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