Patent
1991-01-30
1999-02-02
Treat, William M.
395392, 395566, 395581, 395588, 39580016, 39580018, 39580021, 39580026, 39580027, 395676, 39580025, G06F 1582
Patent
active
058676791
ABSTRACT:
A parallel computer system includes a plurality of processors, each of which is placed in data communication with an interconnecting network. Pairs of a data signal and a data identification code, predetermined for the data signal, are received by each processor and stored in a memory. Structure is provided for reading a data signal belonging to one of the pairs having a data identification code designated by a data readout instruction.
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Hamanaka Naoki
Muramatsu Akira
Nagashima Shigeo
Nakagoshi Junji
Nakao Kazuo
Beall Fay Sharpe
Hitachi , Ltd.
Treat William M.
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