Parallel processor system

Details Parallel processor system Parallel processor system

2001-05-03

2003-05-20

Coleman, Eric (Department: 2183)

Electrical computers and digital processing systems: processing

Processing architecture

Array processor

C712S011000

Reexamination Certificate

active

06567909

ABSTRACT:

TECHNICAL FIELD
The present invention generally relates to parallel processor systems, and more particularly to a parallel processor system which is suited for constructing a mutual connection network which carries out encoding of audio and image data and signal processing on computer graphics and the like.
BACKGROUND ART
With respect to the processor system, there are demands to carry out the signal processing at a high speed and economically. One method of satisfying such demands is to improve the processor performance. However, when this method is employed and the processor performance exceeds a certain threshold value, the costs of hardware and development greatly increase as compared to the improvement of the processor performance. For this reason, in order to realize an extremely high-speed processor, it is necessary to balance various tradeoffs. For example, the improvement of the silicon technology reduces the micron rule to enable reduction of the chip size and reduced power consumption, but the restrictions on signal synchronization and propagation delay become severe such that the time and effort required for the design become extremely large.
On the other hand, as another method of improving the performance of the processor system, there is a method which employs a parallel processor system structure. In the parallel processor system, two or more processors are connected in parallel. In this case, by using a plurality of processors which at least have certain speeds, it is possible to distribute the load among the plurality of usable processors. For example, when a single processor system which is formed by a single processor and a parallel processor system which is formed by a plurality of similar processors are compared, the parallel processor system cannot simply carry out twice the number of processes that can be processed by the single processor system, but the parallel processor system can process more processes in parallel per unit time as compared to the single processor system. In other words, when carrying out the same amount of processes per unit time, the parallel processor system can effectively utilize a more economical processor technology compared to the single processor system. In addition, the parallel processor system has an advantage in that the system scale can be modified by adjusting the number of processors depending on the application environment.
However, in the parallel processor system, it is necessary to realize a cooperative process among the processors by constructing a mutual connection network among the processors. The structure of this mutual connection network is important, because the performance of the entire parallel processor system becomes close to “(processing performance of a unit processor)×(number of processors)” or, “less than or equal to the processing performance of a unit processor” in a worst case, depending on this structure.
Conventionally, there are various connection formats for the mutual connection network, including a total connection type shown in
FIG. 1
, a parallel bus type shown in
FIG. 2
, a ring type shown in
FIG. 3
, a mesh type shown in
FIG. 4
, and an n-cube type shown in
FIG. 5
, for example. When these connection formats for the mutual connection network are categorized generally by function, each connection format is formed by processor nodes PN each having a processor and a communication link, communication paths CP for making communication, and cluster switches CS each connecting three or more communication paths CP.
Next, conditions for making a bandwidth between each two processor nodes PN become equal to W, that is, conditions for making a bandwidth of the communication path CP between the processor node PN and the cluster switch CS become equal to (P−1)×W, where P denotes the number of processor nodes PN, will be compared for the total connection type, the parallel bus type and the ring type connection formats shown in
FIGS. 1 through 3
.
First, performances of the communication paths CP of these connection formats will be compared. In the case of the total connection type connection format shown in
FIG. 1
, since an independent communication path CP connects between each two processor nodes PN, the bandwidth of each communication path CP becomes equal to W. In the case of the parallel bus type connection format shown in
FIG. 2
, because each two processor nodes PN are connected via a common communication path CP, the bandwidth of the common communication path CP becomes equal to P×W. Further, in the case of the ring type connection format shown in
FIG. 3
, when the bandwidths of the communication paths CP between non-adjacent processor nodes PN are averaged, the bandwidth of each communication path CP becomes equal to (P−1)×W. Accordingly, the total connection type connection format is more economical than the other two, in that a low-performance communication path CP can be used.
On the other hand, with regard to the structure of the cluster switch CS is observed, only the bandwidth (P−1)×W needs to be controlled in the case of the total connection type connection format, but a bandwidth larger than (P−1)×W needs to be controlled in the case of the parallel bus type and the ring type connection formats because a communication between the non-adjacent processor nodes PN and passing through the cluster switch CS is also generated. However, when the number of communication paths CP connected to the cluster switch CS is observed, the number is three in the case of the parallel bus type and the ring type connection formats regardless of the number of processor nodes PN, while the number is P in the case of the total connection type connection format. For this reason, in the case of the total connection type connection format, the structure of the cluster switch CS becomes more complex as the number of processor nodes PN of the parallel processor system increases, and it becomes difficult to realize the structure for a large number of processor nodes PN, both costwise and technically.
Therefore, the total connection type connection format is superior when the number of processor nodes PN of the parallel processor system is small, but the structures of the parallel bus type and the ring type connection formats become more advantageous technically as the number of processor nodes PN increases.
In the case of the parallel bus type and the ring type connection formats, however, the distance between the processor nodes PN, that is, the number of passing cluster switches CS, becomes a problem as the number of processor nodes PN of the parallel processor system increases. In the case of the total connection type connection format, the number of passing cluster switches CS is two regardless of the number of processor nodes PN. But in the case of the parallel bus type connection format, the number of passing cluster switches CS is equal to the number of P of processor nodes PN for a maximum path. Further, in the case of the ring type connection format, the number of passing cluster switches CS is equal to INT(P/2+1) for a maximum path, where INT denotes an integer value obtained by ignoring fractions. Moreover, although a communication delay may be estimated to be a fixed delay in the case of the total connection type connection format, the communication delay is not fixed in the case of the parallel bus type and the ring type connection formats and this communication delay may greatly affect the performance of the entire parallel processor system.
Hence, as the number of processors of the parallel processor system increases, it is not always possible to construct an efficient mutual connection network using the total connection type, the parallel bus type or the ring type connection format.
The mesh type connection format shown in FIG.
4
and the n-cube type connection format shown in
FIG. 5
have been proposed to solve the above described problems. In the case of the mesh type and the n-cube type connection formats, the connect

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