Boots – shoes – and leggings
Patent
1994-01-28
1996-04-02
Coleman, Eric
Boots, shoes, and leggings
364229, 3642293, 3642291, 3642705, 364DIG1, G06F 1580
Patent
active
055049184
DESCRIPTION:
BRIEF SUMMARY
FIELD OF THE INVENTION
The present invention concerns a board multiprocessor system architecture of elementary processors organized according to a parallel structure.
This invention can be used in a large numbers of applications for processing data and more particularly data relating to image elements (or pixels).
BACKGROUND OF THE INVENTION
The processings of conventional images comprise several levels of processing. An expert in this field will normally consider three levels of processing: sensors so as to deduce from this a filtered image (this may be regarded as an "ionic processing" when this concerns the processing of images); the useful symbols of the processing by transforming the data with an iconic format to a symbolic format (a processing also known as "symbolic processing"). transforming them so as to deduce from them the actions to be carried out. This level contains the intelligence of the processing of images as it contains in particular the shape recognition algorithms and the decision shots.
The low level is used in a large number of SIMD (Single Instruction Stream Multiple Data Stream) type multiprocessors systems, that is processors carrying out a given operation on different items of data.
On the other hand, the high level is used in MIMD (Multiple Instruction Stream Multiple Data Stream) type multiprocessors systems, that is complex structures allowing for parallelism both as regards the data and the instructions.
As for the mid-level, this is rarely parallelized. However, four approaches have been put forward shown on the accompanying FIGS. 1A, 1B, 1C and 1D.
Thus, on these same figures, four approaches of parallel architectures have been shown enabling the mid-level processing to be carried out.
FIG. 1A represents the "Bottom Up" architecture. In this architecture, the possibilities of the low level multiprocessor system BN are increased so as to support the operations of the mid-level MN. An independent multiprocessors system is able to process the operations of the high level HN.
FIG. 1B represents the "Top Down" architecture. In this architecture, the possibilities of the multiprocessors system carrying out the operations of the high level HN are modified so as to integrate with them the processings of images of the mid-level MN. An independent multiprocessor system is able to support the operations of the low level BN.
FIG. 1C has shown an architecture which could be known as a "unified architecture" in which a single system supports the three levels of processing, namely the high level processing HN, the mid-level processing MN and the low level processing BN, the multiprocessor being reconfigured during processing.
FIG. 1D has shown an architecture which could be known as "natural architecture" and which includes a specific mid-level MN processing system. In this architecture, each level has its own structure. It is therefore easy to move from a dimension structuring 2 (case of an image) to a symbolic structuring. However, this architecture proves to be extremely cumbersome as it requires three systems, each system being needed to support a different processing level.
The unified and Top Down architectures are difficult to implement: in fact, the low level and the mid-level can be integrated in SIMD mode systems but this mode is unsuitable for high level processings.
Thus, it seems preferable to select a Bottom Up architecture in which the low and mid-level can be implanted in a given SIMD mode system, the high level then being implanted in a second system working in the MIMD mode.
Architectures of Bottom Up type multiprocessor systems are already known, these systems mostly carrying out effectively the low level processing but are difficult to implement for mid-level processing.
Such a system has been described in the patent application published under the number FR-A-2 623 310. This concerns an image processing multiprocessor system known as SYMPATI. However, this system does not exhibit optimal performances, as shall be seen subsequently.
SYMPATI is a distributed memory
REFERENCES:
patent: 5208900 (1993-05-01), Gardner
patent: 5218709 (1993-06-01), Fijany
IBM Technical Disclosure Bulletin, vol. 26, No. 5, Oct. 1983, "Multiplex Interface Control . . . " J. R. Volk.
IBM Technical Disclosure Bulletin, Oct. 1983, "Multiplex Interface Control in a Closed-Ring Network", Volk, vol. 26 No. 5, pp. 2272-2275.
Collette Thierry
Es-Safi Hassane
Kaiser Josef
Schmit Renaud
Coleman Eric
Commissariat a l''Energie Atomique
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