Electrical computers and digital processing systems: processing – Processing architecture – Distributed processing system
Reexamination Certificate
2006-04-18
2006-04-18
Thomson, William (Department: 2194)
Electrical computers and digital processing systems: processing
Processing architecture
Distributed processing system
C718S102000
Reexamination Certificate
active
07032099
ABSTRACT:
A parallel processor capable of establishing synchronization among programs executed in parallel, wherein a processor element suspends its processing and enters a waiting state when a wait instruction “sleep” is executed in a user program Prg_d and resumes the processing by releasing the above waiting state based on execution of a wait release instruction “cont(Prg_d)” by another processor element and wherein the latter processor element executes a next instruction without suspending its processing after executing the wait release instruction “cont(Prg_d)”.
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Kananen Ronald P.
Opie George L.
Rader & Fishman & Grauer, PLLC
Sony Corporation
Thomson William
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