Parallel processor memory transfer system using parallel transfe

Details Parallel processor memory transfer system using parallel transfe Parallel processor memory transfer system using parallel transfe

1995-03-03

1996-12-03

Ellis, Richard L.

395481, G06F 1576, G06F 1338

Patent

active

055817777

ABSTRACT:
A massively parallel processor is provided with a plurality of clusters. Each cluster includes a plurality of processor elements ("PEs") and a cluster memory. Each PE of the cluster has associated with it an address register, a stage register, an error register, a PE enable flag, a memory flag, and a grant request flag. A cluster data bus and an error bus connects each of the stage registers and error registers of the cluster to the memory. The grant request flags of the cluster are interconnected by a polling network, which polls only one of the grant request flags at a time. In response to a signal on the polling network and the state of the associated memory flag, the grant request flag determines an I/O operation between the associated data register and the cluster memory over the cluster data bus. Both data and error bits are associated with respective processor elements. The sequential memory operations proceed in parallel with parallel processor operations. The sequential memory operations also may be queued. Addressing modes include direct and indirect. In direct address mode, a PE addresses its own address space by appending its PE number to a broadcast partial address. The broadcast partial address is furnished over a broadcast bus, and the PE number is furnished on a cluster address bus. In indirect address mode, a PE addresses either its own address space or that of other PEs in its cluster by locally calculating a partial address, then appending to it either its own PE number or that of another PE in its cluster. The full address is furnished over the cluster address bus.

REFERENCES:
patent: 3800289 (1974-03-01), Batcher
patent: 3812467 (1974-05-01), Batcher
patent: 3863233 (1975-01-01), Eddey et al.
patent: 3936806 (1976-02-01), Batcher
patent: 3987419 (1976-10-01), Morrill et al.
patent: 4314349 (1982-02-01), Batcher
patent: 4316244 (1982-02-01), Grondalski
patent: 4447877 (1984-05-01), Grondalski
patent: 4462073 (1984-07-01), Grondalski
patent: 4481580 (1984-11-01), Martin et al.
patent: 4591981 (1986-05-01), Kassabou
patent: 4598400 (1986-07-01), Hillis
patent: 4709327 (1987-11-01), Hillis et al.
patent: 4719621 (1988-01-01), May
patent: 4773038 (1988-09-01), Hillis et al.
patent: 4783738 (1988-11-01), Li et al.
patent: 4791641 (1988-12-01), Hillis
patent: 4797815 (1989-01-01), Moore
patent: 4805091 (1989-02-01), Thiel et al.
patent: 4805173 (1989-02-01), Hillis et al.
patent: 4827403 (1989-05-01), Steele, Jr. et al.
patent: 4852048 (1989-07-01), Morton
patent: 4860249 (1989-08-01), Nicely et al.
patent: 4873626 (1989-10-01), Gifford
patent: 4891787 (1990-01-01), Gifford
patent: 4980854 (1990-12-01), Donaldson et al.
patent: 5010476 (1991-04-01), Davis
patent: 5060186 (1991-10-01), Barbagelata et al.
patent: 5165023 (1992-11-01), Gifford
Comcon 90 26 Feb. 1990, San Francisco, CA, US pp. 20-24 XP146160 Tom Blank "The Maspar MP-1 architecture" * the whole document *.
Comcon 90 26 Feb. 1990, San Francisco, CA, US pp. 73-81 XP146168 Creve Marple "Merlin: the superglue for multicomputer systems" * the whole document *.
Proceeding of the 1989 International Conference on Parallel Processing, vol. 1, 8 Aug. 1989, The Pennsylvania State University Press, pp. 142-150, L. Wittie "Merlin: Massively Parallel Heterogeneous Computing".
Processing Supercomputing '89, 13 Nov. 1989, Reno, Nevada, U.S., pp. 476-484 XP90914 Y. K. Park "DASP: A General-Purpose Mimd Parallel Computer Using Distributed Associative Processing".
McLeod, J., "Look out, Cray: Here comes a super-priced supercomputer," Electronics, Aug. 1989, pp. 83-86.
Perry, T. et al., "Supercomputer experts predict expansive growth," IEEE Spectrum, Feb. 1989, pp. 26-33.
Stone, H., "Discrete Mathematical Structures and Their Applications", Science Research Associates, Inc., 1973, pp. 165-179.

Affiliated with

Also associated with

Rating

Parallel processor memory transfer system using parallel transfe does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Parallel processor memory transfer system using parallel transfe, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Parallel processor memory transfer system using parallel transfe will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-795389