Parallel processor

Details Parallel processor Parallel processor

1998-08-07

2002-07-23

Patel, Ramesh (Department: 2121)

Data processing: generic control systems or specific application

Generic control system, apparatus or process

Plural processors

C700S002000, C700S012000, C700S067000, C712S020000, C712S203000, C712S215000, C707S793000, C707S793000, C707S793000, C709S237000, C709S238000, C710S108000, C710S112000, C370S400000, C370S409000

Reexamination Certificate

active

06424870

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a parallel processor having a plurality of nodes interconnected via a network, the nodes transferring messages therebetween. More particularly, the invention relates to a parallel processor wherein a node returns an acknowledge message upon receipt of a message.
BACKGROUND ART
One way of ensuring high reliability in message communication between nodes making up a parallel processor is for a receiving node (i.e., a node that has received a message) to return an acknowledge message to a transmitting node (which transmitted the message) acknowledging the receipt of each message.
If the transmitting node fails to receive within a predetermined period of time an acknowledge message from the receiving node, and if the original message was lost for some reason, the transmitting node may again generate the same message for retransmission to the receiving node, thus making up for the lost message. Upon receipt of an acknowledge message from the receiving node, the transmitting node will release from its memory a storage area which, containing the transmitted message and control information necessary for transmission of the message, has been protected against changes in anticipation of possible message re transmission.
FIG. 7
shows a typical constitution of a conventional parallel process or. In
FIG. 7
, n odes
1
,
2
, . . . N are interconnected via a network
70
. Each node, connected to the network
70
in a way exemplified by the node
1
, comprises a network interface controller
700
for control of communication with the network; a processor
720
; a memory
730
for storing software and various items of information; and a memory controller
710
for controlling access requests to the memory
730
from the network interface controller
700
and processor
720
.
In the parallel processor of the above constitution, suppose that the node
2
sends a message to the node
1
. In such a case, the processor
720
of the node
1
conventionally executes message processing software upon receipt of the message. Once executed, the software prepares transmit data and a message transmission control word based on the content and the status of the message received from the node
2
, generates an acknowledge message in accordance with the prepared transmit data and message transmission control word, and returns the generated acknowledge message to the node
2
. More specifically, when the node
2
transmits a message to the node
1
, the network interface controller
700
of the node
1
receives the message. The network interface controller
700
then checks to see if the received message is destined for its own node. If the message is found to be destined for its own node, the controller
700
stores the message into a predetermined area of the memory
730
. Having stored the received message, the network interface controller
700
interrupts and notifies the processor
720
of the message reception. In turn, the processor
720
starts executing software for processing the received message. In carrying out the software, the processor
720
checks that the message currently stored in the memory
730
was normally received, verifies who sent the message, and performs other suitable interpretations to prepare a message transmission control word (needed to return an acknowledge message in response to the received message) and to generate an acknowledge message accordingly to be sent back to the transmitting node.
In the prior art, as described, normal reception of a message by the receiving node entails executing a number of steps for returning an acknowledge message: interrupting and notifying the processor of the receipt of the message, generating an acknowledge message, scheduling the message returning software, and having the message interpreted by the scheduled software. With these steps carried out, it takes a considerable time for the receiving node to return an acknowledge message to the transmitting node. This requires the transmitting node to maintain for an extended period of time the transmit data and the message transmission control word that were stored in memory, in anticipation of possible message retransmission. During that period, the transmitting node cannot re-allocate this memory for storing any other transmit data or message transmission control word for transmitting other messages. This may impede progress of message communication processing. Even if the bottleneck is bypassed by enlarging the memory capacity, provision of a sizable memory can pose other problems.
The need to prepare and return an acknowledge message causes the receiving node to have greater processor overheads than if no acknowledge message is returned. If the receiving node fails to receive a message normally, the node cannot return an acknowledge message except when message receipt information can be retained. Until an acknowledge message is received, the transmitting node cannot take measures to redress the error.
It is therefore an object of the present invention to provide a parallel processor comprising a plurality of nodes wherein any node, having received a message, returns an acknowledge message without recourse to its processor carrying out a message returning process.
The major benefit available from such a parallel processor is threefold. First, the transmitting node side may release at an earlier stage its storage area set aside to accommodate the transmit data and message transmission control word in anticipation of possible message retransmission. Second, the receiving node has its processor subjected to less burden when returning an acknowledge message. Third, the receiving node, if failing to receive a message normally, still returns an acknowledge message in as many cases as possible to the transmitting node so that the latter may handle the error accordingly.
DISCLOSURE OF INVENTION
In carrying out the invention and according to one aspect thereof, there is provided a parallel processor comprising at least two nodes and a network for interconnecting the nodes which communicate messages therebetween over the network; wherein each of the nodes has an interface controller for processing transmission and reception of messages to and from the network, and a processor for sending a message transmission request to the interface controller; and wherein the interface controller, independently of the processor, prepares and returns an acknowledge message based on predetermined information included in the message received from the network.


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patent: 5826095 (1998-10-01), Jordan
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patent: 6012053 (2000-01-01), Pant et al.
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patent: 1-163861 (1989-06-01), None
patent: 4-92952 (1992-03-01), None

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