Parallel processing units on a substrate, each including a colum

Details Parallel processing units on a substrate, each including a colum Parallel processing units on a substrate, each including a colum

1990-12-14

1994-06-28

Dixon, Joseph L.

Boots, shoes, and leggings

364DIG1, 364229, 3642292, G06F 1300

Patent

active

053255003

ABSTRACT:
Parallel processing circuitry on a substrate includes an array of memory elements in rows and columns. Row select circuitry can select the memory elements in any of the rows. Each column has respective processing circuitry to access its memory elements. The columns' processing circuitry can perform operations on data in parallel, so that each column and its processing circuitry form a processing unit. Data can be transferred to or from any of the columns. A column register can be connected so that data from a first column can be read, stored, and then written into a second column. Or a permutation network with connecting lines can be set up so that each connecting line can transfer data from one column to another. The column register can be connected to a shift register for transferring data to or from an external connection. Or the connecting lines of the permutation network can be set up for transferring data to or from the external connection. The processing circuitry of all the columns are connected to receive signals that control their operations in parallel. The processor can be used to perform value assignment search, with each processing unit storing data indicating a respective combination of values. Initially, an initial processing unit has a valid bit in its memory set to indicate that its combination of values is consistent with constraints. Then data from one processing unit can be copied to another, and modified either in the source or in the destination processing unit to obtain two respective subcombinations of values, with the valid bit remaining set. The processing units can perform operations in parallel to determine whether their respective combinations are consistent with a constraint. If a combination is inconsistent, the respective valid bit is cleared.

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