Parallel processing system with processor array having memory sy

Details Parallel processing system with processor array having memory sy Parallel processing system with processor array having memory sy

1986-12-17

1989-10-10

Shaw, Gareth D.

Boots, shoes, and leggings

3642426, 364254, 3642543, G06F 700

Patent

active

048736260

ABSTRACT:
A highly-parallel processing system in which a number of processing elements are interconnected by a network, and are also connected to a system bus and are controlled by a central processing unit. Each processing element includes a memory, and all of the memories in the processing elements form at least part of the memory available to the CPU. The processing elements normally execute programs in MIMD mode, and the CPU or another unit can interrupt them to execute a SIMD instruction. The network allows for transmission of variable length messages and also for combining messages when received at a common processing element.

REFERENCES:
patent: 3979728 (1976-09-01), Reddaway
patent: 4365292 (1982-12-01), Barnes et al.
patent: 4435758 (1984-03-01), Lorie et al.
patent: 4622632 (1986-11-01), Tanimoto et al.
"Introduction to Data Level Parallelism", Thinking Machines Technical Report 86.14 Apr., 1986.

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